Search results | J. Murrey Atkins Library

Title: CORE TEMPERATURE AWARE THREAD SCHEDULING IN HETEROGENEOUS MULTI-CORE ARCHITECTURE
Author: Jadhav, Pratik
Date Created: 2014
Description: Along with the evolution of heterogeneous multi-core architectures, advanced thread scheduling algorithms for maximizing system efficiency are needed. As power density increases with technology, core temperature variations can cause bottlenecks in...

Title: CORE TEMPERATURE AWARE THREAD SCHEDULING IN HETEROGENEOUS MULTI-CORE ARCHITECTURE
Author: Jadhav, Pratik
Date Created: 2014
Subjects--Topical: Electrical engineering
Description: Along with the evolution of heterogeneous multi-core architectures, advanced thread scheduling algorithms for maximizing system efficiency are needed. As power density increases with technology, core temperature variations can cause bottlenecks in...

Title: Cache-Aware Implementation of Compressed Sensing Reconstruction using Walsh-Hadamard Transform on a Multicore Architecture
Author: Ramgopal, Aneesh
Date Created: 2014
Description: The recent development of the compressed sensing (CS) theory has given rise to several algorithms being proposed for signal acquisition and reconstruction. Implementing these algorithms are computationally demanding and pose several challenges for...

Title: Cache-Aware Implementation of Compressed Sensing Reconstruction using Walsh-Hadamard Transform on a Multicore Architecture
Author: Ramgopal, Aneesh
Date Created: 2014
Subjects--Topical: Electrical engineering, Computer engineering
Description: The recent development of the compressed sensing (CS) theory has given rise to several algorithms being proposed for signal acquisition and reconstruction. Implementing these algorithms are computationally demanding and pose several challenges for...

Title: Design of Fault Tolerant Systems
Author: Walker, Benjamin
Date Created: 2012
Description: This research designs a Fault Tolerant Control (FTC) approach that compensates for both actuator and sensor faults by using multiple observers. This method is shown to work for both linear time-variant and linear time-invariant systems. This work ...

Title: Design of Fault Tolerant Systems
Author: Walker, Benjamin
Date Created: 2012
Subjects--Topical: Electrical engineering
Description: This research designs a Fault Tolerant Control (FTC) approach that compensates for both actuator and sensor faults by using multiple observers. This method is shown to work for both linear time-variant and linear time-invariant systems. This work ...

Title: FAULT-TOLERANT DESIGN FOR CONTINUOUS REAL-TIME MONITORING AND MODULATION OF THE HUMAN BRAIN
Author: Acharya, Ipsita
Date Created: 2015
Description: An era of brain implantable devices has been ushered in recent years. These devices are currently being used to treat neurological disorders such as Parkinson's depression and epilepsy and are increasingly being proposed for a wide range of neurol...

Title: FAULT-TOLERANT DESIGN FOR CONTINUOUS REAL-TIME MONITORING AND MODULATION OF THE HUMAN BRAIN
Author: Acharya, Ipsita
Date Created: 2015
Description: An era of brain implantable devices has been ushered in recent years. These devices are currently being used to treat neurological disorders such as Parkinson's depression and epilepsy and are increasingly being proposed for a wide range of neurol...

Title: FAULT-TOLERANT DESIGN FOR CONTINUOUS REAL-TIME MONITORING AND MODULATION OF THE HUMAN BRAIN
Author: Acharya, Ipsita
Date Created: 2015
Subjects--Topical: Electrical engineering, Biomedical engineering
Description: An era of brain implantable devices has been ushered in recent years. These devices are currently being used to treat neurological disorders such as Parkinson's depression and epilepsy and are increasingly being proposed for a wide range of neurol...

Title: Thread Mapping Using System-Level Model for Shared Memory Multicores
Author: Mitra, Reshmi
Date Created: 2015
Description: Exploring thread-to-core mapping options for a parallel application on a multicore architecture is computationally very expensive. For the same algorithm, the mapping strategy (MS) with the best response time may change with data size and thread c...

Title: Thread Mapping Using System-Level Model for Shared Memory Multicores
Author: Mitra, Reshmi
Date Created: 2015
Subjects--Topical: Computer engineering, Mathematics
Description: Exploring thread-to-core mapping options for a parallel application on a multicore architecture is computationally very expensive. For the same algorithm, the mapping strategy (MS) with the best response time may change with data size and thread c...